1. Field of the Invention
The present invention relates to a scanning circuit apparatus for testing a large scale integrated circuit (LSI).
2. Description of the Related Art
In a general scanning circuit apparatus for testing a large scale integrated circuit (LSI), scanning data for test can be supplied to an internal register disposed in the large scale integrated circuit so as to judge whether the large scale integrated circuit is defective or not by finding a defect of the large scale integrated circuit in an operating process thereof. In this general scanning circuit apparatus, a multiplexer disposed in each of a portion for inputting data and a portion for inputting a clock signal in a flip-flop circuit. A normal clock signal and normal input data are selected by the multiplexers at the time of a normal operation of the scanning circuit apparatus. A scanning clock signal and scanning data are selected by the multiplexers at a scanning time of the scanning circuit apparatus. These clock signals and data are selected by a testing control signal. When an input terminal for inputting an asynchronous setting signal, an input terminal for inputting an asynchronous resetting signal, or the input terminals for inputting both the asynchronous setting and resetting signals are disposed in the flip-flop circuit, a gate is disposed before the setting or resetting signal input terminal. In a normal operating state of the scanning circuit apparatus, the setting and resetting signals are validated by the testing control signal. The setting and resetting signals are invalidated by the testing control signal at the scanning and testing times of the scanning circuit apparatus.
With respect to a latch cell, a latch circuit on a master side is used at the normal operating time of the scanning circuit apparatus. A latch circuit for scan on a slave side is also used in addition to the latch cell on the master side. A scanning data output portion of one flip-flop circuit is connected to a scanning data input portion of another scanning circuit. The scanning data output portion and the scanning data input portion are operated as one shift register at the testing time of the scanning circuit apparatus.
In the above general scanning circuit apparatus, the scanning data are generally scanned by only the scanning clock signal. When the data of test results are shifted, it is necessary to reduce a time difference caused by a shift in phase of the scanning clock signal supplied to each scanning circuit for test. This shift in phase is called a clock skew. When the above time difference is large, there is a possibility that the scanning data are destroyed when the scanning data are scanned. For example, a test data output terminal of a scanning register is connected to a scanning data input portion of another scanning register. When the scanning registers are automatically wired in a gate array, etc., there is a case in which the registers are greatly separated from each other. In such a case, a phase shift is caused with respect to a scanning clock signal supplied to each of scanning clock signal input terminals of the scanning registers, thereby causing the above-mentioned clock skew in a certain case.
When the scanning operation is performed at the testing time, the above data of the test results are shifted by latching the scanning data outputted from a previous scanning register in a rise of the scanning clock signal. However, when the above clock skew is caused and the scanning clock signal supplied to the previous scanning register rises faster than a scanning clock signal supplied to a subsequent scanning register, the scanning data outputted from the previous scanning register are changed before the scanning data of the previous scanning register are latched. Therefore, it is impossible to perform a normal shifting operation.
As mentioned above, the setting and resetting operations of a general scanning circuit having setting and resetting terminals are validated at a normal operating time thereof by using a testing control signal. These setting and resetting operations are invalidated at the scanning and testing times of the general scanning circuit by using the testing control signal. Namely, at the scanning and testing times, the transmissions of setting and resetting signals to be inputted to the registers are compulsorily interrupted before these signals are inputted to the registers. Therefore, at the scanning and testing times, it is impossible to test an error in operation of the scanning circuit caused by errors in the setting and resetting signals. In other words, the setting and resetting signals cannot be checked. Accordingly, it is necessary to test the operation of the scanning circuit in a normal operating state thereof with respect to the setting and resetting signals.